Current AI scale-up architectures rely heavily on high-speed PAM4-class SerDes and copper-based interconnects. As scale-up network needs grow in domain size and extend beyond a single rack, new challenges emerge—key among them are the need for high-bandwidth, low-latency connectivity often demanding tens of terabits per second at the accelerator package interface. These escalating bandwidth demands for both accelerator-to-accelerator communication and memory expansion place stringent constraints on energy efficiency (pJ/bit), bandwidth density (Tbps/mm), link quality (BER and reliability), latency, and cost points. To address these challenges, novel interconnections are increasingly being considered, with a growing push toward integrating these solutions close to or directly into the accelerator package.
To this end, this symposium discusses the latest trends and advancements in photonic technologies for AI scale-up systems such as VCSELs, Silicon photonics, and other emerging technologies, as well as packaging techniques such as co-packaged optics (CPO), on-board optics (OBO) and pluggable optics (LPO/LRO) for low-power solutions.
In particular, industry experts from cloud and infrastructure companies, foundries, and manufacturing as well as technology developers, come together to discuss the current developments and the remaining challenges with respect to electro-photonic integration, packaging and assembly, manufacturing and reliability, towards enabling the development and at scale deployment of photonic solutions in AI clusters.
Organizers
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Tad Hofmeister
Google LLC
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Fotini Karinou
Microsoft
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Vijay Vusirikala
Arista Networks, Inc.