17 Mar 2026
11:45 - 12:15
Expo Theater III
As AI workloads drive Ethernet speeds to 224G SerDes and 1.6T links, data center reliability challenges are no longer dominated by silicon logic or protocol design, but by interconnect behavior under compounded stress. Nearly 80% of failures occur at interconnects, where a single weak link can stall GPU clusters, inflate job completion times, and cost millions in lost compute cycles.
While traditional validation methods have focused on PHY compliance and synthetic traffic testing, large-scale AI deployments are revealing reliability gaps that only emerge at the intersection of physical margin, functional behavior, and real workload dynamics.
In this panel discussion, industry leaders will examine why validation practices that were sufficient at 400G and 800G increasingly fall short at AI scale. Drawing on real deployment experience, the panel will explore how previously acceptable assumptions around BER, link bring-up, and cable integrity can mask latent failure modes, leading to stalled GPU clusters, inflated job completion times, and costly debug cycles.
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