17 Mar 2026
16:30 - 18:30
Room 515A
Current AI scale-up architectures rely heavily on high-speed PAM4-class SerDes and copper-based interconnects. As scale-up network needs grow in domain size and extend beyond a single rack, new challenges emerge—key among them are the need for high-bandwidth, low-latency connectivity often demanding tens of terabits per second at the accelerator package interface. These escalating bandwidth demands for both accelerator-to-accelerator communication and memory expansion place stringent constraints on energy efficiency (pJ/bit), bandwidth density (Tbps/mm), link quality (BER and reliability), latency, and cost points. To address these challenges, novel interconnections are increasingly being considered, with a growing push toward integrating these solutions close to or directly into the accelerator package.
To this end, this symposium discusses the latest trends and advancements in photonic technologies for AI scale-up systems such as VCSELs, Silicon photonics, and other emerging technologies, as well as packaging techniques such as co-packaged optics (CPO), on-board optics (OBO) and pluggable optics (LPO/LRO) for low-power solutions.
In particular, industry experts from cloud and infrastructure companies, foundries, and manufacturing as well as technology developers, come together to discuss the current developments and the remaining challenges with respect to electro-photonic integration, packaging and assembly, manufacturing and reliability, towards enabling the development and at scale deployment of photonic solutions in AI clusters.
Organizers
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Tad Hofmeister
Google LLC, United States
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Fotini Karinou
Microsoft, United States
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Vijay Vusirikala
Arista Networks, Inc., United States
Speakers
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Ram Huggahalli
Microsoft, United States
Optical technologies and high radix switches motivate multi-rack scale-up domains. However, there are system considerations involving link performance, physical integration, RAS, and fiber management. Further, system design must target high operational efficiency with real workloads.
Ram Huggahalli is a Principal Hardware Engineer at Microsoft and leads the Platform and Physical Technologies team in enabling new technologies for future AI and General-Purpose compute platforms. Among the various exciting projects, his team is evaluating optical interconnect technologies for AI Scale-up communication and memory disaggregation use cases. Ram has previously contributed to Microsoft's Cobalt 100 and Cobalt 200 processors as an IO and platform architect. Prior to Microsoft, Ram was the lead performance architect for Intel's large-scale HPC interconnect products. Ram has over 20 patents and graduated with an MS in Electrical Engineering and Engineering Management at the University of Missouri.
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CP Hung
ASE, Taiwan
The rapid evolution of AI has ushered new era computational demands, necessitating paradigm shift in data center architecture. This presentation will explore the opportunities and challenges of advanced packages with both electrical and optical interconnects
Dr. CP Hung, IEEE Fellow, is currently Vice President of Corporate R&D, at ASE Group, responsible for broad range of next-generation integrated technologies. He holds 354 patents encompassing IC packaging structure, characterization, design, substrate, test and system miniaturizing solutions. Furthermore, with 142 conference and journal papers published.
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Manish Mehta
Broadcom, United States
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Rob Stone
Meta, United States
Future AI scale-up infrastructure will transition from electrical to optical interconnects to enable larger domains, rack disaggregation, and higher bandwidth. This talk will share end user perspectives on deployment challenges and evolving requirements.
Rob Stone is a HPC network engineer in the networking strategy and architecture team at Meta. Rob has over 25 years of industry experience bringing networking and optics technologies to market and has held both technical and managerial positions at Broadcom, Intel, Infinera, Emcore, Skorpios Technologies, and Bandwidth 9. Rob holds a D.Phil. in Physics from The University of Oxford.
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Matt Sysak
Lumentum, United States
This presentation will discuss low power, low-cost, high reliability, and ultra-high density sensing VCSEL interconnects for scaleup applications. Sensing VCSEL technology leverages well established supply chain, including manufacturing, test, a history of high-volume deployments.
Matt Sysak is the Global Chief Technology Officer at Lumentum. He has more than 20 years of experience with Silicon Photonics, IIIV optical components and systems, along with CMOS validation, test, and packaging. Previously, Matt was the VP of laser and Platform Engineering at Ayar Labs where he was responsible for leading laser strategy, customer engagements, and backend engineering. Prior to Ayar Labs, Matt held several senior positions at Intel, where his graduate research on Hybrid Silicon Lasers was commercialized and has now shipped millions of units.
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Jason Wildt
Jabil, United States
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Phil Winterbottom
Celestial.AI, United States
Silicon Photonics is set to permeate the connectivity infrastructure of data centers over the next few years. With a little thought now into the architecture of CPO now we can position the technology for deep integration into switches, CPUs and AI accelerators in the future.
Phil is the CTO at Celestial AI, where he works across all aspects of applying silicon photonics to AI interconnects. Prior to joining Celestial AI, Phil founded several startups and led them from initial concept to revenue. He began his career at Bell Labs in the Computer Science Research Center, where he worked on the Plan 9 OS, parallel compilers, and high-performance networking. In recognition of his contributions to operating systems, he was named a Bell Labs Fellow in 1999.