As >200 GBd transceivers emerge as the next major step for data-center networks, scaling to 400 Gb/s per lane exposes constraints that go far beyond bandwidth of electrical and optical components alone. This workshop examines whether higher symbol rates, new modulation schemes, or architectural shifts can realistically deliver higher rates per lane considering tight limits on components, electrical traces, packaging, power, latency, and DSP complexity. The session will explore device materials and components and link them to system‑level tradeoffs that ultimately determine what can scale and what can ship.
Key questions the workshop will focus on:
● Is 400 Gb/s per lane technically and commercially feasible on a timeline that matters for DCN deployment?
● Is 400 Gb/s per lane universe answer to every network domain?
● Will data rate per lane continue to increase beyond 400 Gb/s?
● Which component becomes the bottleneck at higher lane rates: SerDes, drivers, modulators, photodiodes, TIAs, packaging, clocks, or electrical traces?
● Can incumbent platforms (silicon photonics, InP) scale beyond ~200 GBd, or are advanced modulation materials required?
● Is the adoption of completely novel technology, such as Wired THz radios, a possible solution?
● Does PAM-4 still scale to 400 Gb/s per lane, or do higher-order PAM formats offer a more robust path?
● Do electrical and optical gearboxes, including mixed-PAM domains, reduce overall system risk or simply redistribute complexity and power?
● Are linear optics approaches (LPO/XPO/NPO) viable at 400 Gb/s per lane, and under what link and packaging assumptions?\
● Can CPO support 400 Gb/s per lane? If yes, what technology choices and ecosystem changes are required?
Organizers
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Aaron Maharry
Lucidean Inc., United States
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Ann Margareth Rosa Brusin
Politecnico di Torino, Italy
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Noriaki Kaneda
Coherent Corp., United States
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Qian Hu
Nokia, United States