Symposia: Disaggregating the AI Infrastructure: Co-Designing Compute and Memory Beyond Copper

AI infrastructure is shifting from monolithic, tightly packaged compute toward disaggregated compute and memory resources linked by optical interconnects. Two disaggregation efforts are advancing largely in isolation: (i) Die-to-die optical interconnects for GPU compute panels, competing with classical co-packaging on energy and cost-per-bit and (ii) Optically pooled memory, as an alternative to CXL-attached DRAM, competing on bandwidth and reach beyond copper limits.  Each raises its own questions: panel-scale topology and switching fabrics on one side, coherency and latency tiering on the other. This symposium focuses on the underexplored space between them: co-designing compute and memory disaggregation together, where topology, switching fabrics, coherency strategy, and orchestration must be jointly optimized rather than solved separately.

Two sessions bring device, systems, and hyperscaler perspectives together to debate whether one optical platform can serve both domains, whether CXL 4.0 closes the gap before optics matures, whether disaggregated compute and memory can match tightly-coupled latency, and who ends up owning that co-design: chip vendors, integrators, or hyperscalers.

Questions to Be Debated

1. At what scale (die, package, board, or rack) does optical interconnect become unavoidable, and does that threshold differ for compute vs. memory?
2. Can one optical platform serve both compute and memory disaggregation, or do the two need separate solutions?
3. Does CXL 4.0 close the bandwidth gap for near-term AI workloads, or does pooled optical memory arrive first?
4. Can optically disaggregated memory and compute reach latencies competitive with tightly-coupled alternatives (on-package HBM, co-packaged compute), or is disaggregation a permanent secondary tier?
5. Which topology (any-to-any, hierarchical, or hybrid) and switching fabric (static or reconfigurable) best supports compute and memory disaggregation together?
6. Who owns compute-memory co-design: chip vendors, integrators, or hyperscalers?
7. Can a unified control plane manage both without compromising the latency advantage of optics?