Trey Greer, NVIDIA, USA
Clint Schow, UCSB ECE, USA
The power efficiency of short (<100 m) datacenter optical links has become increasingly important, and pJ/bit has become a ubiquitous figure of merit. However, it is difficult or often impossible to assess and compare true end-to-end power dissipation for various link architectures. Optical link papers often stop power accounting at the optical transducer edges, and do not include the power costs of (de) serialization and clock distribution on the PIC. Furthermore, as we progress toward co-packaged optics, we need a consistent framework for estimating the power of various electrical links to the host ASIC. This panel has a broad scope that extends from systems to devices, and is targeted at beginning to build consensus on how to consistently and quantitatively account for end-to-end power in optical links.
Our goal is to provide researchers with the tools they need to fit their link components into an overall link power consumption budget. We hope to start discussions on the power costs of:
● FEC power per bit vs BER.
● DFE, FFE, and receiver linear EQ.
● Clock distribution and data (de)serialization at various symbol rates.
● 'Gear Boxes’ for converting data stream formats between optical vs electrical layers.
● The electrical links for CPO vs NPO vs pluggable.
● Optical losses at package connections and within PICs that drive up laser power.
Andreas Bechtolsheim, Arista, USA
Rom Gray, Nividia Research, USA
Thomas Lijeberg, Intel, USA
Alexander Rylakov, Nokia, Canada