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Xelic Announces 100G Staircase EFEC Core for FPGA Applications


24 March 2015


Xelic Announces 100G Staircase EFEC Core for FPGA Applications

March 24, 2015 – Xelic, a leading provider of Optical Transport Networking (OTN) intellectual property is pleased to announce the immediate availability of their XCO4EFECSC core. This core provides 100G Enhanced Forward Error Correction (EFEC) capability that is interoperable with Cortina Systems HG-FEC (Staircase) ITU Proposal B13-06-98 ITU COAST-OHI-2013-039 COM 15-C328-E July 2013. The core is available for FPGA applications and has been optimized for  Xilinx UltraScale FPGA’s.  
“The  Xilinx  optimized version takes advantage of Xilinx’s UltraScale DSP architecture to provide a very efficient implementation without sacrificing performance” said Mark Grabosky, founding partner and Director of Engineering at Xelic. “We have tested the core in hardware to ensure interoperability with Cortina’s devices.”  
To learn more about the XCO4EFECSC and Xelic’s other IP products visit

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